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The CAN-PCIe/402-FD is a PC board designed for the PCIe bus that features one or two electrically isolated CAN FD interfaces according to ISO 11898-2 via DSUB9 connectors. Equipped with up to two CAN FD interfaces the board is available as low profile versions. In the CAN-PCIe/402-B4-FD version 4 CAN FD interfaces can be connected via one 37-pin DSUB connector. The CAN FD interfaces are designed according to ISO 11898-1:2015. They are driven by the ISO 16845:2004 certified esdACC (esd advanced CAN Core), implemented in the Intel FPGA. All CAN FD versions are fully backwards compatible with CAN and can also be used in Classical CAN applications. The FPGA supports bus mastering (first-party DMA) to transfer data to the host memory. This results in a reduction of overall latency on servicing I/O transactions in particular at higher data rates and a reduced host CPU load.

The CAN-PCI/402-2-FD is a PC board designed for the PCI bus that features two electrically isolated high-speed CAN FD interfaces according to ISO 11898-1:2015. The CAN FD interfaces are driven by the ISO 16845:2004 certified esdACC implemented in the Intel® FPGA. With a higher bit rate in the data phase in combination with the increase of efficiency by a higher number of user-data bytes, CAN FD offers a higher data throughput while maintaining the benefits of Classical CAN. The board is fully backwards compatible with CAN and can be also used in Classical CAN applications. The FPGA supports bus mastering (firstparty DMA) to transfer data to the host memory. This results in a reduction of overall latency on servicing I/O transactions in particular at higher data rates and a reduced host CPU load. Due to the usage of MSI (Message Signaled Interrupts) the CAN-PCI/402-2-FD can be operated for example in Hypervisor environments. The board provides high resolution hardware timestamps.

The CAN-M.2/402-2-FD is an M.2 Card, that features two electrically isolated CAN FD interfaces. The optional adapter CAN-PCIeMini/402-DSUB comes with a DSUB9 connector, selectable on-board CAN termination and an adapter cable. CAN-M.2/402-2-FD is fully backwards compatible with CAN and can also be used in Classical CAN applications. The independent CAN nets are driven by the ISO 16845:2004 certified esdACC (esd Advanced CAN Core) implemented in the Intel FPGA. The FPGA supports bus mastering (first-party DMA) to transfer data to the host memory. This results in a reduction of overall latency on servicing I/O transactions, in particular at higher data rates and a reduced host CPU load. Due to the usage of MSI (Message Signaled Interrupts) the CAN-M.2/402-2-FD can be operated for example in Hypervisor environments. The CAN-M.2/402-2-FD provides high resolution 64-bit hardware timestamps for CAN messages. A wide range of software support and customization is available on request.

The CAN-PCIeMini/402-2 is an add-in PCI Express Full-Mini Card, that features two electrically isolated CAN High-Speed interfaces. The PCI Express® Mini Card comes with two CAN FD interfaces. There is also a version that can be used for extended temperature range. The optional adapter CAN-PCIeMini/402-DSUB9 comes with a DSUB9 connector, selectable on board CAN termination and an adapter cable. All CAN FD versions are fully backwards compatible with CAN and can also be used in Classical CAN applications. The independent CAN nets are driven by the ISO 16845:2004 certified esdACC (esd Advanced CAN Core) implemented in the Altera FPGA. The FPGA supports bus mastering (firstparty DMA) to transfer data to the host memory. This results in a reduction of overall latency on servicing I/O transactions in particular at higher data rates and a reduced host CPU load. Due to the usage of MSI (Message Signaled Interrupts) the board can be operated for for example in Hypervisor environments.

The ECS-PCIe/FPGA is an EtherCAT Slave Controller board designed for the PCI Express bus. It utilizes a Beckhoff IP-Core which is implemented in an Altera® FPGA and configured for 8 FMMUs, 8 Sync Managers, 60 kB DPRAM and 64 bit Distributed Clocks. The FPGA connects between the PCI Express bus and the two Ethernet interfaces on the front panel. Because of this simple hardware topology and the use of a “soft” controller the design offers a maximum of flexibility. The PCI Express system can act as an I/O node. An EtherCAT master can use several EtherCAT protocols like CoE, FoE and EoE to communicate with this EtherCAT slave device. Via pin header connectors equipped on the ECS-PCIe/FPGA 36 3.3 V LVTTL I/Os are available, including the signals from the EtherCAT Slave Controller: 2x Sync and 2x Latch for system synchronization. Device drivers for Windows® and Linux® with documentation and EtherCAT slave examples are included in the scope of delivery. Other (real time) OS on request.