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The ECS-PCIe/FPGA is an EtherCAT Slave Controller board designed for the PCI Express bus. It utilizes a Beckhoff IP-Core which is implemented in an Altera® FPGA and configured for 8 FMMUs, 8 Sync Managers, 60 kB DPRAM and 64 bit Distributed Clocks. The FPGA connects between the PCI Express bus and the two Ethernet interfaces on the front panel. Because of this simple hardware topology and the use of a “soft” controller the design offers a maximum of flexibility. The PCI Express system can act as an I/O node. An EtherCAT master can use several EtherCAT protocols like CoE, FoE and EoE to communicate with this EtherCAT slave device. Via pin header connectors equipped on the ECS-PCIe/FPGA 36 3.3 V LVTTL I/Os are available, including the signals from the EtherCAT Slave Controller: 2x Sync and 2x Latch for system synchronization. Device drivers for Windows® and Linux® with documentation and EtherCAT slave examples are included in the scope of delivery. Other (real time) OS on request.